Process for forming a dual damascene structure

ABSTRACT

The invention describes a method for forming a dual damascene structure. An etch stop layer ( 150 ) is formed on a dielectric layer ( 140 ). A second dielectric layer ( 160 ) is formed on the etch stop layer ( 150 ) and an ARC layer ( 170 ) is formed the second dielectric layer. A first trench ( 185 ) and a second trench ( 195 ) are then simultaneously formed in the first and second dielectric layers ( 140 ) and ( 160 ) respectively.

This application is a Continuation of Ser. No. 09/901,331 filing dateJul. 9, 2001 now U.S. Pat. No. 6,605,540.

FIELD OF THE INVENTION

The invention is generally related to the field of semiconductor devicesand fabrication and more specifically to a method for forming a dualdamascene structure.

BACKGROUND OF THE INVENTION

To increase the operating speed, high performance integrated circuitsuse copper interconnect technology along with low dielectric constantdielectrics. Currently the dual damascene method is the most widely usedmethod for forming copper interconnects. A typical dual damasceneprocess is illustrated in FIGS. 1( a)–1(c). As shown in FIG. 1( a), afirst etch stop layer is formed over a dielectric layer 10 and a copperline 20. A first dielectric layer 40, a second etch stop layer 50, and asecond dielectric layer 55 are formed over the first etch stop layer. Apatterned layer of photoresist is then formed and used to pattern theetching of the first trench 57. Following the etching of the firsttrench 57, a backside anti-reflective coating (BARC) layer 60 is formed.During the formation of the BARC layer 60, additional BARC material 65is formed in the trench 57. The additional BARC material 65 is necessaryto protect the bottom surface of the trench during the etching of thesecond trench 58. This is illustrated in FIG. 1( b). A portion of theadditional BARC 65 is removed during the etching process. Following theetching of the second trench 58, trench liner material is formed 80 andcopper 90 is used to fill both trenches as illustrated in FIG. 1( c).

There are a number of important issues concerning the use of theadditional BARC 65 to mask the trench. Some of the more important ofthese are non-uniformity in dense and isolated structures, punchingthrough the first etch stop layer 30 during the etching process, defectscaused by the BRAC material etc. These is therefore a need for animproved process that overcomes the issues associated with the use ofthe BARC trench masking material 65.

SUMMARY OF THE INVENTION

The present invention describes a process for forming dual damascenestructures. In particular, a first dielectric layer is formed over asilicon substrate containing one or more electronic devices. A firstetch stop layer is then formed over this first dielectric layer and asecond dielectric layer is then formed over the first etch stop layer. Asilicon oxynitride anti-reflective coating layer is then formed over thesecond dielectric layer and a first trench is etched to a first depth inthe second dielectric layer and the first dielectric layer. A secondtrench is etched in the second dielectric layer while simultaneouslyetching the first trench in the first dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIGS. 1( a)–1(c) are cross-sectional diagrams illustrating the priorart.

FIGS. 2( a)–2(d) are cross-sectional diagrams illustrating an embodimentof the instant invention.

DETAILED DESCRIPTION OF THE INVENTION

The invention will now be described with reference to FIGS. 2( a)–2(d).It will be apparent to those of ordinary skill in the art that thebenefits of the invention can be applied to other structures where adual damascene process is utilized.

The requirement of higher clock rates has lead to the use of copper toform the metal interconnect lines in integrated circuits. In addition tothe use of copper, dielectric layers such as organosilicate glass (OSG)(dielectric constant ≃2.6) and florosilicate glass (FSG) are currentlybeing used to take advantage of the lower dielectric constant of suchmaterials compared to silicon dioxide. In an embodiment of the instantinvention, a first etch stop layer 130 is formed over a copper layer 120and a dielectric layer 100 as shown in FIG. 2( a). The dielectric layer100 is formed over a silicon substrate which contains one or moreelectronic devices such as transistors, diodes, etc. These electronicdevices will typically be part of an integrated circuit. The dielectriclayer 100 may be formed over various portions of an integrated circuit.The copper layer 120 represents a portion of the copper interconnect ofthe integrated circuit. The first etch stop layer 130 may comprisesilicon nitride (SiN), silicon carbide (SiC), or any suitable material.Following formation of the first etch stop layer 130, a first dielectricfilm 140 is formed over the etch stop layer 130. In an embodiment of theinstant invention this first dielectric layer 140 comprisesflorosilicate glass (FSG) In addition to FSG any suitable dielectricmaterial may be used to form the first dielectric layer 140. Followingthe formation of the first dielectric layer 140, a second etch stoplayer 150 may or may not be formed. This second etch stop layer 150comprises a material selected from the group consisting of siliconnitride (SiN), silicon carbide (SiC), or any combination of layers ofthese or other suitable materials. Following the formation of the secondetch stop layer 150, a second dielectric layer is formed. In anembodiment of the instant invention this second etch stop layercomprises FSG, OSG or any suitable dielectric material. Following theformation of the second dielectric layer 160, a layer of anti-reflectivecoating (ARC) 170 is formed as shown in FIG. 2( a). In an embodiment ofthe instant invention this ARC layer 170 comprises silicon oxynitride.An important property of the ARC layer 170 is that no light be reflectedduring the photolithographic process. Such an ARC film can be formedusing silicon oxynitride with the following atomic percentages, silicon(30%–55%), oxygen (20%–50%), nitrogen (2%–17%), and hydrogen (7%–35%).Following the formation of the ARC layer 170, a photoresist layer isformed and patterned 180. The ARC layer 170, the second dielectric layer160 and the second etch stop layer 150 are etched using a multi-stepetch process to form a first trench 185 as illustrated in FIG. 2( a). Inan embodiment of the instant invention the silicon oxynitride layer canbe etched using a CF₄ based plasma etch process. In particular a 300 Ato 2000 A silicon oxynitride film can be etched using CF₄ with flowrates of 50 sccm–120 sccm, oxygen with flow rates of 1 sccm–9 sccm,argon with flow rates of 200 sccm–500 sccm, and power of about 1000 W to2000 W. One advantage of using the silicon oxynitride film is thatthinner layers of photoresist (i.e. less than 3000 A) can be used. Thisleads to improved resolution over the thicker resist films necessary incurrent processes. For cases where FSG is used to form the seconddielectric layer 160, an argon (200 sccm–400 sccm), CH₂F₂ (10 sccm–35sccm), and oxygen (9 sccm–34 sccm) based plasma etch process can be usedwith power levels of approximately 1000 W. Finally to etch through thesecond etch stop layer 150, a C₅F₈ (5 sccm–13 sccm), argon (300 sccm–650sccm), and oxygen (4 sccm–13 sccm) etch process with a power level ofapproximately 1500 W can be used. The depth of the first trench 187 isvariable. The embodiment represented in FIG. 2( a) shows the bottomsurface of the trench below the second etch stop layer. In general therequired depth of the first trench depends on the thickness of thedielectric layers 140 and 160 and the required depth of the secondtrench.

Following the formation of the first trench 185, the remainingphotoresist film 180 is removed and another patterned photoresist filmis formed 190 which will be used to define the width of the secondtrench. This is illustrated in FIG. 2( b). Using the photoresist film asan etch mask, the exposed regions of the ARC layer 170 is etched. Forthe case where a silicon oxynitride ARC layer is used the layer can beetched using a CF₄ based plasma etch process. In particular a 300 A to2000 A silicon oxynitride film can be etched using CF₄ with flow ratesof 50 sccm–120 sccm, oxygen with flow rates of 1 sccm–9 sccm, argon withflow rates of 200 sccm–500 sccm, and power of about 1000 W to 2000 W.During the subsequent etching of the dielectric layers 160 and 140 theARC layer will serve as a hardmask. Dielectric layers 160 and 140 arethen etched simultaneously with a second trench 195 being formed in thesecond dielectric layer 160 and the first trench 185 etched in the firstdielectric layer 140 as shown in FIG. 2( c). The etching of the secondtrench 195 will stop on the second etch stop layer 150 (if present), andthe etching of the first trench 185 in the first dielectric layer 140will stop on the first etch stop layer 130.

During the formation of the second trench 195 in the second dielectriclayer 160, the etching of the first trench 185 is completed in the firstdielectric layer. The first etch stop layer 130 beneath the firstdielectric layer 140 is therefore not exposed to the entire secondtrench etching processes. This eliminates the need for the BARCprotective layer currently used in the art.

Following the formation of both trenches (185 and 195) the exposedregion of the first etch stop layer 130 is removed and a liner film 200is formed as shown in FIG. 2( d). The formation of the liner film isfollowed by a copper deposition and chemical mechanical polishingprocess which results in the copper layer 210 shown in FIG. 2( d).Typically the copper layer 210 is formed by first forming a thick layerof copper followed CMP processes to remove the excess copper.

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the inventionwill be apparent to persons skilled in the art upon reference to thedescription. It is therefore intended that the appended claims encompassany such modifications or embodiments.

1. A method for forming a dual damascene structure, comprising:providing a silicon substrate containing one or more electronic devices;forming a first dielectric layer of a first thickness over said siliconsubstrate; forming a first etch stop layer over said first dielectriclayer; forming a second dielectric layer of a second thickness over saidfirst dielectric layer; forming an anti-reflective coating layer oversaid second dielectric layer prior to etching of a first trench; etchingsaid first trench in said second dielectric layer; simultaneouslyetching a second trench to a first depth in said second dielectric layerand etching said first trench in said first dielectric layer wherein thefirst depth is approximately equal to the second thickness; removing thefirst etch stop layer at a bottom portion of the first trench; forming aliner film in the first trench and the second trench; and forming acontiguous copper layer in the first trench and the second trench. 2.The method of claim 1 wherein said anti-reflective coating layercomprises silicon oxynitride.
 3. The method of claim 1 wherein firstetch stop layer is formed with material selected from the groupconsisting of silicon carbide and silicon nitride.
 4. The method ofclaim 1 wherein said first dielectric layer is OSG.
 5. The method ofclaim 1 wherein said second dielectric layer is OSG.
 6. A method forforming a copper filled dual damascene structure, comprising: providinga silicon substrate containing one or more electronic devices; forming afirst dielectric layer of a first thickness over said silicon substrate;forming a first etch stop layer over said first dielectric layer;forming a second dielectric layer of a second thickness over said firstdielectric layer; forming a silicon oxynitride anti-reflective coatinglayer over said second dielectric layer prior to etching a first trenchin said second dielectric layer; etching said first trench to a firstdepth in said second dielectric layer and said first dielectric layerwherein the first depth is greater than the thickness of said seconddielectric layer; simultaneously etching a second trench to a seconddepth in said second dielectric layer and etching said first trench insaid first dielectric layer wherein the second depth is approximatelyequal to the second thickness; removing the first etch stop layer at abottom portion of the first trench; forming a liner film in the firsttrench and the second trench; and forming a contiguous copper layer inthe first trench and the second trench.
 7. The method of claim 6 whereinsaid silicon nitride anti-reflective coating layer comprises 30 to 50atomic percent of silicon, 20 to 50 atomic percent of oxygen, 2 to 17atomic percent of nitrogen, and 7 to 35 atomic percent of hydrogen. 8.The method of claim 6 wherein first etch stop layer is formed withmaterial selected from the group consisting of silicon carbide andsilicon nitride.
 9. The method of claim 6 wherein said first dielectriclayer is OSG.
 10. The method of claim 6 wherein said second dielectriclayer is OSG.
 11. A method for forming a dual damascene structure,comprising: providing a silicon substrate containing one or moreelectronic devices; forming a first etch stop layer over the siliconsubstrate; forming a first dielectric layer over the first etch stoplayer; forming a second etch stop layer over the first dielectric layer;forming a second dielectric layer over the second etch stop layer;forming an anti-reflective coating layer over the second dielectriclayer prior to etching of a first trench; etching the first trenchhaving a first width through the anti-reflective coating layer, thesecond dielectric layer, and the second etch stop layer; concurrentlyetching a second trench having a second width greater than the firstwidth through the second dielectric layer down to the second etch stoplayer and etching the first trench through the first dielectric layerdown to the first etch stop layer, wherein the second trench overliesthe first trench; removing the first etch stop layer at a bottom portionof the first trench; forming a liner film in the first trench and thesecond trench; and forming a contiguous copper layer in the first trenchand the second trench.